Does uart_int.v testcase run successfully? :: Bugtracker

Does uart_int.v testcase run successfully?

Information:
Type :: BUG
Status :: OPENED
Assigned to ::

Description:
I tried to run the supplied testcase, "uart_int.v", but it fails in ModelSim. The message in uart_interrupts_verbose.log is shown below:

Time: 5734521200 (testbench.tx_fifo_status_changing)
*E, Bit 5 of LSR register not '1'!

I just wanted to verify that someone has successfully run the testcase before I spend any more time troubleshooting it.

Regards,
Dalton

Comments:

Guenzel, Robert	Nov 6, 2007
Well, the again. That simply got the simulation up and running, but it didn't fix the bug you reported. Sorry.

Guenzel, Robert	Nov 6, 2007
I encountered an equal problem, which was related to the wb_sel_i decoding. The testcase (i.e. the wb_master) is always setting wb_sel_i to 4'hF which leads to masking off the lower two bits of the wb_addr (see uart_wb.v lines 293 and 301), because the case statements hit the default case. My solution was to change the lines 293 and 301 to: default: wb_adr_int_lsb = wb_adr_is[1:0]; If you dislike this 'hack', simply make the wb_master use the correct wb_sel_i values. best regards Robert

Guenzel, Robert

Nov 6, 2007

I encountered an equal problem, which was related to the wb_sel_i decoding.
The testcase (i.e. the wb_master) is always setting wb_sel_i to 4'hF which leads to masking off the lower two bits of the wb_addr (see uart_wb.v lines 293 and 301), because the case statements hit the default case.

My solution was to change the lines 293 and 301 to:

default: wb_adr_int_lsb = wb_adr_is[1:0];

If you dislike this 'hack', simply make the wb_master use the correct wb_sel_i values.

best regards
Robert